High NA EUV Lithography Benefits, Challenges, and the Path to Continued Scaling

As the semiconductor industry begins the 2nm manufacturing ramp and accelerates R&D toward the sub-2nm node, high numerical aperture (NA) extreme ultraviolet (EUV) lithography is emerging as a critical enabler of continued device scaling. By improving resolution and enhancing pattern fidelity, high NA EUV lithography is expected to play a central role in future semiconductor manufacturing. Here, we discuss the benefits and challenges of high NA EUV lithography as well as how the collaborative NY Creates semiconductor R&D ecosystem is poised to accelerate innovation at 2nm and beyond.

Advantages of High NA EUV Lithography

High numerical aperture (high NA) extreme ultraviolet (EUV) lithography is widely recognized as the next major advancement in semiconductor patterning technology. By increasing the projection optics numerical aperture from 0.33 to 0.55 while maintaining the 13.5nm EUV wavelength, high NA EUV lithography significantly improves imaging resolution and contrast, pattern fidelity, and process simplification, enabling continued transistor scaling beyond current leading-edge technology nodes. 

The primary benefit of high NA EUV lithography is enhanced lithographic resolution, as it allows for substantial improvement in the ability to print smaller features with increased image contrast. This enhanced optical performance enables patterning of dense line-space structures at pitches previously unattainable with conventional EUV lithography, extending the scaling roadmap for advanced logic and memory devices. Further, it improves process windows and dimensional control, resulting in better critical dimension uniformity and reduced edge-placement error [1,2]. These characteristics are essential for future gate-all-around (GAA) transistor architectures and complementary field-effect transistor (CFET) technologies, where patterning precision directly impacts device performance and yield.

High NA EUV lithography also reduces multi-patterning requirements. As device geometries shrink, conventional EUV increasingly relies on double or multiple patterning techniques to achieve the desired pitches, introducing additional lithography, etch, and metrology steps, which increases process complexity, cost, cycle time, and defect opportunities. High NA EUV enables many of these critical layers to be printed using fewer exposures, simplifying process integration and improving overall manufacturing efficiency, which may contribute to higher yield by minimizing overlay-related defects and cumulative process variation.

From a manufacturing perspective, high NA EUV lithography can improve overall cost effectiveness despite higher equipment investment. While high NA scanners represent a significant capital expenditure, the reduction in multi-patterning steps, lower process complexity, fewer mask requirements, and potential yield improvements can offset these costs at advanced technology nodes. As a result, high NA EUV is expected to become an economically attractive solution for high-volume manufacturing (HVM) of leading-edge semiconductor products. Furthermore, it strengthens the long-term scalability of semiconductor roadmaps by providing a viable path for continued feature size reduction beyond the capabilities of current EUV platforms, extending Moore's Law and enabling future generations of high-performance computing, artificial intelligence, and memory products. 

Challenges of High NA EUV Lithography

While high NA EUV lithography offers significant advantages for continued semiconductor scaling, the technology also introduces a new set of technical, manufacturing, and economic challenges. Achieving HVM with high NA EUV lithography requires advances across exposure systems, materials, masks, metrology, computational lithography, and ecosystem readiness. These challenges must be addressed through broad industry collaboration before the technology can be fully leveraged in future technology nodes. 

Stochastic Defects and Photoresist Limitations

A significant challenge facing high NA EUV lithography is the management of stochastic defects. As feature dimensions continue to shrink and pattern pitches approach the atomic scale, the limited number of EUV photons available during exposure can lead to random variations in resist chemistry and pattern formation. These stochastic effects manifest as line-edge roughness (LER), line-width roughness (LWR), microbridges, and missing or broken features that directly impact device yield and reliability. This is compounded by the need for photoresists that simultaneously provide high sensitivity, low roughness, and high resolution. Traditionally, improvements in one of these parameters often result in degradation of another, making optimization difficult for resist suppliers. Developing next-generation resist systems capable of meeting high NA resolution requirements remains a major research focus within the lithography ecosystem. 

Mask and Imaging Complexity

High NA EUV lithography introduces an anamorphic optical design that differs substantially from current 0.33 NA EUV systems. The anamorphic architecture increases imaging performance but reduces the exposure field size, creating additional constraints for chip layout and mask design. Designers may need to partition large features across multiple exposures or optimize layouts to accommodate the reduced field dimensions. Mask three-dimensional effects also become increasingly significant at high NA. Because EUV masks are reflective multilayer structures rather than transmissive photomasks, shadowing effects and angle-dependent reflectivity can introduce image distortions that affect pattern fidelity. Correcting these effects requires sophisticated optical proximity correction (OPC), computational lithography, and mask engineering techniques, increasing overall design complexity and computational requirements. 

Overlay and Process Integration Challenges

Advanced logic and memory technologies increasingly require precise alignment between multiple lithography and etch operations. As feature dimensions continue to shrink, overlay errors represent a larger percentage of the critical dimension, making process control increasingly difficult. High NA EUV places tighter requirements on overlay performance and process integration than previous lithography generations. Furthermore, the successful implementation of high NA EUV requires the co-optimization of lithography, etch, deposition, metrology, and inspection processes. Improvements in exposure capability alone are insufficient if the surrounding manufacturing ecosystem cannot achieve equivalent gains in precision and defect reduction. This necessitates extensive collaboration between equipment suppliers, materials vendors, and semiconductor manufacturers. 

Metrology and Inspection Requirements

Shrinking feature dimensions increase the difficulty of accurately measuring and characterizing critical patterns. Existing metrology and inspection tools must evolve to detect increasingly smaller defects, quantify stochastic variation, and characterize nanoscale structures with greater precision. Defect inspection becomes particularly challenging because many stochastic defects are both rare and randomly distributed, requiring new inspection methodologies and data-driven analytics to identify yield-limiting mechanisms. The development of advanced actinic inspection systems, high-resolution e-beam metrology tools, and machine-learning-based defect classification systems is therefore essential for successful high NA deployment. Without corresponding advances in metrology, process optimization and yield improvement become substantially more difficult. 

Cost and Manufacturing Readiness and Workforce Challenges

High NA EUV scanners are among the most sophisticated and expensive manufacturing systems ever developed. The acquisition cost of a high NA exposure system, together with associated infrastructure, cleanroom modifications, and supporting process equipment, represents a significant capital investment for semiconductor manufacturers. Beyond equipment costs, industry-wide readiness remains a challenge. Successful deployment requires a mature ecosystem of materials suppliers, mask manufacturers, software providers, metrology companies, universities, and workforce development programs. Developing and maintaining a workforce capable of operating, optimizing, and supporting these systems is a critical challenge for the industry. Collaborative research environments that provide access to high NA tools before production deployment are therefore essential for reducing risk and accelerating learning cycles.

Collaborative Semiconductor R&D Ecosystems

Creates is a not-for-profit corporation serving as the U.S. epicenter for semiconductor R&D, education and workforce development, and high-tech economic advancement. Creates owns and operates the largest, most advanced non-profit semiconductor R&D center in North America, the two-million-square-foot Albany NanoTech Complex, along with additional facilities across New York State. Creates hosts 3,000 experts and support staff focused on accelerating innovation to commercialization in areas including semiconductors, quantum technologies, advanced memory, integrated photonics, devices for neuromorphic computing and AI, advanced packaging and heterogeneous integration, and more. 

A focal point of such efforts is Creates’ High NA EUV Lithography Center [3,4,5], which leverages a $1 billion investment from New York State to enable an additional $9 billion in industry investment with partners, including Micron, Applied Materials, IBM, Tokyo Electron, and others. Creates’ High NA EUV Lithography Center offers standard NA, and soon, high NA EUV lithography R&D and prototyping capabilities for development at the 2nm node and beyond that do not exist anywhere else in North America within an accessible semiconductor R&D ecosystem. Importantly, this Center will accelerate R&D for sub-2nm nodes with key capabilities including some of the most innovative high NA EUV lithography technology ever produced: ASML’s TWINSCAN EXE:5200B. This tool is being installed inside Creates’ new NanoFab Reflection (NFR) building, which features 50,000 square feet of state-of-the-art cleanroom space, complementing the existing advanced EUV capabilities at Creates, supporting partner growth and critical initiatives. Installation has also already begun in NFR for Tokyo Electron’s leading-edge 300mm wafer coater/developer system, designed to support the next generation of semiconductor manufacturing. This tool, the CLEAN TRACK™ LITHIUS Pro DICE™ [6], applies and processes the highly sensitive photoresist layers on silicon wafers, required for researchers to fabricate the minute patterns needed for the next generation of advanced processors, memory, sensors, and more.

Conclusion

The introduction of high NA EUV lithography, combined with co-located deposition, etch, metrology, and materials capabilities, extends the industry’s ability to continue device scaling into the angstrom era. However, realizing its potential requires coordinated advances in materials, masks, computational lithography, metrology, and process integration. The collaborative, public-private nature of our Albany NanoTech Complex positions Creates well to lead lab-to-fab-to-field efforts in key focus areas for the semiconductor industry. As high NA EUV lithography moves into a central role in semiconductor manufacturing, collaborative R&D environments will become increasingly important for validating new materials, technologies, and device architectures. By bringing together equipment suppliers, materials innovators, academic researchers, and semiconductor manufacturers, Creates is positioned to help accelerate the transition from sub-2nm R&D to HVM. 

References

1. J. van Schoot, “This Machine Could Keep Moore’s Law on Track: High-Numerical-Aperture EUV Lithography”, IEE Spectrum, Jul. 2023
2. imec, “The Case for High-NA EUV: Unlocking the next Era of Chip Manufacturing,” 2026
3. NY Creates. https://ny-creates.org/.
4. D. Anderson, “Meeting 2nm Node Challenges: Overcoming Scaling Limits Through High NA EUV and Ecosystem Collaboration,” Semiconductor Digest, 2026
5. NY Creates, “NY Creates’ High NA Extreme Ultraviolet Lithography Center.” https://ny-creates.org/technology/euv-lithography-center/.
6. NY Creates, “Governor Hochul Announces $10 Billion Partnership to Bring Next-Generation Research and Development Center to NY Creates’ Albany NanoTech Complex.” https://ny-creates.org/governor-hochul-announces-10-billion-partnership-to-bring-next-generation-research-and-development-center-to-ny-creates-albany-nanotech-complex/.