JEDEC Solid State Technology Association Previews Next-Generation LPDDR6 Enhancements for AI and Data Centre Workloads

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, previewed a set of new features planned for incorporation into the next version of its JESD209‑6 LPDDR6 standard. Building on the foundational JESD209‑6 published in July 2025, JEDEC’s JC‑42.6 Subcommittee has been working to enhance the next version of the standard to extend LPDDR6 beyond mobile platforms to support selected data centre and accelerated computing workloads seeking a power‑efficient, high‑capacity memory platform.

Planned features for the upcoming LPDDR6 update include:

• Narrower per-die interface (x6) enables higher capacities: With the move to a non-binary interface width, from x16 to x24, the inclusion of x12 and an additional x6 sub-channel mode allows more dies per package and higher memory capacities per component and per channel, a critical enabler for AI-scale memory footprints.
• Flexible metadata carve‑out intended to minimise impact to peak data throughput, giving data centre customers the option to balance user capacity and metadata needs according to their specific reliability requirements.
• 512 GB density on the horizon: LPDDR6 is expected to unlock densities beyond the current LPDDR5/5X maximum, a capability designed to address the ever-growing memory capacity requirements of AI training and inference workloads.
• LPDDR6 SOCAMM2 module standard in development: JEDEC is actively working on an LPDDR6-based SOCAMM2 module standard, which is being designed to carry the compact, serviceable module form factor forward and offer a clear upgrade path from today’s LPDDR5X SOCAMM2 modules.

LPDDR6 PIM standard in development: JEDEC is also nearing completion of a standard for LPDDR6 Processing‑in‑Memory (LPDDR6 PIM) technology, which complements the broader LPDDR6 roadmap, a next‑generation memory solution intended to address the rapidly increasing performance and energy‑efficiency requirements of edge and data-centre inference workloads. By integrating processing capability directly within LPDDR6 memory, LPDDR6 PIM reduces data movement between memory and compute, enabling higher inference performance and lower power consumption while maintaining the efficiency advantages of LPDDR‑based designs.

“Stay tuned for more details on the next version of LPDDR6 as well as LPDDR6 PIM and LPDDR6 SOCAMM2,” said Mian Quddus, JEDEC Board of Directors Chairman. “The subcommittee continues to evaluate features for inclusion in these standards when they are published.”