AI Moves Deeper into Semiconductor Design as Chipmakers Automate More Development Tasks
From floorplanning and PPA optimisation to RTL generation, verification and software tuning, AI is expanding across the chip-design workflow while engineers continue to guide architecture and specifications.
Artificial intelligence is becoming increasingly involved in semiconductor development, moving beyond individual optimisation tasks to support wider parts of the chip-design process. Electronic design automation (EDA) companies have already introduced machine-learning and reinforcement-learning tools for areas such as floorplanning, placement, routing and power, performance and area (PPA) optimisation. More recent systems are expanding into RTL generation, verification and automated analysis, allowing AI to examine results, identify potential problems and suggest design changes.
This shift is also being seen among major chip developers. Google has used its AlphaChip system to assist with physical design and floorplanning, while Nvidia has developed internal AI systems trained on its own engineering data and hardware-design knowledge. OpenAI has taken the approach further with its Jalapeño custom inference chip, using AI throughout parts of the implementation, verification and optimisation process. OpenAI says AI helped the project move from initial design to tapeout in nine months, including work on arithmetic circuits and repeated design and measurement cycles.
OpenAI has reported measurable improvements from the AI-assisted design process. According to the company, AI-supported implementations improved the performance of selected arithmetic components, while also helping reduce the area occupied by certain matrix and SIMD units. The company has also used its models to optimise software and kernels for Jalapeño, illustrating how AI can increasingly connect chip design with the software that runs on the resulting hardware.
The semiconductor industry is therefore moving towards a more automated design workflow, although human engineers continue to play a central role. Current systems can optimise an architecture, generate or modify portions of RTL, run EDA tools and repeat design iterations, but the fundamental architecture and specifications still require human input. The next stage could see AI systems taking responsibility for a broader combination of architectural exploration, implementation and verification, potentially shortening development cycles as chip complexity continues to increase.
One emerging example is Architect Labs, which has described its Redwood accelerator as an AI-driven co-design project in which human architects establish the specification while AI handles much of the subsequent logic generation, verification and software development. However, Redwood has not yet been produced as a physical ASIC; its reported performance figures are based on an FPGA implementation and a projected chip design. This distinction highlights the current gap between AI-assisted chip development and fully autonomous production silicon.
