Beyond Faster Chips: Why Data Movement Will Shape AI’s Next Chapter in 2027

That approach has worked incredibly well, but as we look toward 2027, it’s becoming clear that adding compute alone won’t sustain the next wave of AI innovation.

The problem is that moving data to those processors, moving it between components, and managing it across complex systems are becoming just as important as the compute itself.

An AI accelerator may have enormous processing capacity, but if it’s waiting for data from memory or another processor, that capacity goes unused. Adding more accelerators can just create more traffic.

This is a challenge for semiconductor designers, and it will be harder to ignore as AI workloads grow and become more complex.

Three developments, in particular, will shape how the industry responds in 2027: a greater emphasis on system-level efficiency, the continued evolution of chiplet-based architectures, and a shift toward designing hardware around the actual flow of data.

1. AI Performance Will Be Measured at the System Level

The semiconductor industry has traditionally relied on processor-level benchmarks to showcase progress. Clock speeds, transistor counts, and peak computational throughput are still useful indicators, but they don’t tell us everything about how a system will perform in practice. AI is revealing the limitations of that approach.

Training large models requires moving enormous amounts of data across processors, memory, and networking infrastructure. Inference introduces its own challenges, particularly as applications become more interactive, multimodal, and reliant on more complex reasoning.

These workloads place different demands on hardware. Some are constrained by available compute, while others are limited by memory bandwidth, latency, or inter-accelerator communication. The bottleneck often shifts with the workload, which matters because the industry’s definition of performance is evolving.

A processor that delivers higher theoretical throughput may not improve application performance if the surrounding architecture cannot keep it supplied with data. Likewise, adding memory capacity or bandwidth may yield limited benefits if the interconnect fabric introduces congestion or unnecessary data transfers. The growing emphasis on energy efficiency makes this even more significant.

According to the International Energy Agency’s 2026 analysis of energy and AI, global data center electricity consumption is projected to increase from about 485 terawatt-hours in 2025 to 950 terawatt-hours by 2030. AI-focused data center consumption is expected to triple during the same period. This creates a practical constraint for the industry. Computing demand can continue to grow quickly, but power availability, cooling capacity, and infrastructure costs cannot scale indefinitely.

In 2027, I expect we’ll see even more attention paid to useful work delivered per watt and per dollar, rather than peak compute performance in isolation.

For AI inference, metrics such as tokens per second, tokens per watt, and cost per token will matter more. Successful architectures will keep computational resources productive while avoiding unnecessary data movement, latency, and/or energy consumption.

3. Chiplets Will Make System Architecture More Important

Chiplets allow designers to combine smaller, specialized components rather than integrating every function onto a single die, enabling the reuse of proven IP, greater manufacturing flexibility, and workload-specific optimization, but also introducing new architectural challenges.

When components that once communicated within a single die are distributed across multiple dies, designers must account for additional interfaces, communication overhead, power requirements, and system-level coordination. A modular architecture doesn’t automatically yield an efficient system.

Consider an AI platform that integrates general-purpose processors, specialized accelerators, high-bandwidth memory, and networking functions. Each component may be optimized individually, but the platform’s performance depends on how effectively those components exchange information.

If the communication architecture becomes a bottleneck, the advantages of specialization can quickly diminish, underscoring why interoperability is so important to the industry.

The Universal Chiplet Interconnect Express (UCIe) Consortium released its 3.0 specification in August 2025, supporting data rates of 48 and 64 GT/s and introducing enhancements to bandwidth density, power efficiency, and system manageability. These developments are meaningful steps toward more scalable multi-die systems. However, standardized interfaces address only part of the problem.

Connecting chiplets is one challenge, but making them work together efficiently is another. Designers still need to determine how traffic should flow between components, how memory should be shared or accessed, how coherency should be maintained where required, and how the architecture should adapt to changing workloads.

The IEEE’s 2026 Heterogeneous Integration Roadmap reinforces the growing importance of coordinating design, manufacturing, packaging, and reliability considerations across complex systems.

We will also see greater emphasis on reusable architectures that can be adapted across products and markets. An edge AI device will have different power, latency, and cost requirements than a large data center, but both can benefit from common architectural principles and reusable building blocks.

The opportunity is to make those systems more configurable without requiring every design to start from scratch, which will require the industry to think beyond individual chiplets and focus on the architecture that integrates them.

3. Data Movement Will Become a First-Class Design Consideration

The most important change heading into 2027 is that semiconductor designers will address data movement earlier.

Historically, significant attention has focused on selecting the right processing elements, defining memory requirements, and building the connectivity needed to integrate those components. However, maintaining this sequence is becoming more difficult.

Data-movement decisions in complex AI systems influence nearly every other aspect of the architecture. They affect latency, bandwidth, power consumption, memory utilization, and ultimately the amount of useful work the processors can perform.

Consider a system with several AI accelerators that share access to memory and other resources. Its effectiveness depends on the bandwidth available at each interface and on the system’s communication patterns.

Where is data generated, where must it go, and how frequently? Can unnecessary transfers be avoided? What happens when components compete for resources? The answers depend on the workload.

An AI training system may require frequent communication and synchronization across many accelerators. An inference platform may prioritize memory-access efficiency, predictable latency, and throughput under varying demand. An automotive or industrial edge system may have strict real-time requirements within a much smaller power envelope. No single interconnect topology or memory architecture optimally addresses every scenario.

That’s why I believe the industry will adopt more design approaches that let architects evaluate data movement earlier, explore more alternative configurations, and understand system-level trade-offs before committing to implementation. Software-driven architecture exploration will be especially valuable here.

Instead of treating interconnected design as a fixed outcome of processor and memory selection, architects can model traffic behavior, evaluate bandwidth and latency requirements, and optimize component communication as part of the broader design process.

This doesn’t eliminate the complexity of modern semiconductor development, but it can help identify architectural limitations when changes are still practical, rather than discovering them late in the design cycle.

The value extends beyond AI data centers. Intelligent computing is becoming more common in vehicles, industrial systems, robotics, and consumer devices, and designers will face the same underlying challenge at different scales: moving the right data to the right place at the right time, with as little overhead as possible. That will remain relevant regardless of which processor architecture, accelerator technology, or manufacturing process ultimately prevails.

What This Means for the Semiconductor Industry in 2027

None of these developments mean that advances in processors or semiconductor manufacturing are becoming less important. Continued innovation in compute, memory, and packaging are still essential, but we should not confuse improvements in individual components with those in complete systems.

The next generation of AI infrastructure will involve more heterogeneous combinations of processors, accelerators, memory technologies, and interconnects. In most cases, these will need to scale across multiple dies, packages, and entire racks.

At the same time, designers will face increasing pressure to control power consumption, manage development costs, and deliver differentiated products more quickly.

These demands are interconnected. A decision that improves peak bandwidth may increase power consumption. A design that minimizes latency may introduce additional implementation complexity. A more modular architecture may improve reuse but may require greater coordination among components. There will always be trade-offs.

As we move into 2027, I expect the conversation to shift from which company can deliver the fastest individual chip to which architectures can deliver the most efficient, scalable, and adaptable computing systems.

The industry has spent decades making processors extraordinarily capable, but it must now become equally sophisticated in how those processors communicate. The future of AI performance will depend on how much compute we can build and how effectively we can put it to work.