How AI-Powered EDA, 2nm Design, and Samsung Foundry Collaboration Are Accelerating Next-Generation AI Chip Development

Q. As AI, multi-die architectures, and advanced process nodes increase design complexity, how is the collaboration between Synopsys and Samsung Foundry helping customers reduce development risk while accelerating time-to-market?

Synopsys plays a mission-critical role as an on-ramp for customers designing AI silicon on Samsung Foundry’s most advanced nodes. Synopsys and Samsung Foundry have a long-standing collaboration that includes an expanding portfolio of production‑ready Synopsys AI-powered EDA tools, certified interface IP, and silicon-based test capabilities on Samsung’s leading-edge process technologies. Together, the companies provide a tightly integrated environment from design to production to help customers reduce development risk, improve design quality, and speed time-to-market for advanced AI and multi-die designs.

Q. AI-powered EDA is becoming a key differentiator in semiconductor design. What measurable benefits are customers achieving from AI-driven automation, and how do you see AI reshaping chip development workflows over the next few years?

Semiconductor engineering is among the most complex and high-stakes scientific endeavours of our time, making it a compelling use case for artificial intelligence. Synopsys pioneered AI as a core capability of modern chip design, from reinforcement learning and GenAI capabilities to agentic AI workflows in development. These capabilities help customers optimise silicon performance, improve efficiency, and accelerate time to market amidst increasing design complexity and shorter development timelines.

For example, Synopsys announced during the Samsung Advanced Foundry Ecosystem (SAFE) Forum 2026 that Synopsys TestMAX™ with AI-assisted automatic test pattern generation (ATPG) technologies (TSO.ai), validated and deployed in collaboration with Samsung Foundry teams, helps reduce test patterns and test cycles up to 20% while preserving fault coverage on SoC and multi-die designs manufactured at Samsung Foundry.

More broadly, Synopsys.ai Copilot capabilities enable semiconductor engineering teams to accelerate development timelines, support significantly more complex designs, and increase engineering velocity. Utilising Synopsys.ai Copilot, documentation searches and script generation that previously took hours now take minutes with the Synopsys workflow assistant application, improving time to solutions for scripts by 2X on average.

Synopsys also continues to pioneer AI capabilities with increasing levels of autonomy across its leading EDA solutions as it builds an open agentic AI stack centred on orchestrated, multiagent workflows to augment human engineers and accelerate highly complex chip design tasks beyond traditional methods.

Q. The industry is moving rapidly towards 2nm-class processes and advanced 3D integration technologies. What are the biggest technical challenges facing customers in this transition, and how are Synopsys’ design and signoff solutions addressing them?

The 2.5D and 3D packaging market is projected to grow at a 26% CAGR to $80.5B by 2033, driven by demand for AI chips, making multiphysics analysis a mission-critical capability needed across the design flow. 

Semiconductor design for these architectures has evolved into a system-level challenge, driving substantial costs and trade-offs. Tightly packed interconnects introduce more pronounced electromagnetic effects, while mechanical stress and process variation can complicate performance and reliability. As complexity increases, these physics-driven constraints—thermal, signal integrity, and power integrity effects—become pervasive, particularly in multi-die designs and advanced (sub-5nm) nodes.

To mitigate late-stage risks for these advanced designs, teams have traditionally relied on conservative guardbanding, often leading to significant overdesign. To put this in perspective, estimates suggest that overdesign of an advanced chip can translate to up to 35% in wasted silicon area, resulting in up to approximately $250 million in optimisation loss,* underscoring the need for early insight into multiphysics effects.  

To address these challenges, Synopsys Multiphysics Fusion solutions integrate EDA and golden signoff multiphysics analysis directly into every stage of design, from exploration to signoff, helping to improve predictability and accelerate convergence for AI and high-performance computing systems.

Q. Multi-die and chiplet-based architectures are expected to play a major role in future AI and high-performance computing systems. How important is design technology co-optimisation (DTCO) in enabling these next-generation platforms?

In multi-die designs, performance, power efficiency, and cost are influenced by complex interactions across multiple dies, interconnects, process nodes, and packaging technologies. This fundamentally shifts optimisation from a single-domain problem to a multi-domain, system-level challenge, driving the importance of co-design and optimisation from DTCO to system technology co-optimisation (STCO).

Samsung Foundry and Synopsys’ long-standing collaboration enables our customers to leverage optimised AI-powered design solutions and multiphysics intelligence across the design and manufacturing flow so they can get their advanced designs to market quickly and with confidence.

Q. Synopsys and Samsung have highlighted improvements in test efficiency, power, performance, and reliability. How critical is closer collaboration between EDA providers, foundries, and IP suppliers in delivering commercially successful advanced-node products?

Reaching production on advanced nodes demands tight collaboration across design and manufacturing. The latest Samsung Foundry and Synopsys collaborations reflect years of deep DTCO engagement and silicon learning between the companies.

For example, through ongoing DTCO initiatives, Synopsys Fusion Compiler™ on Samsung Foundry’s third-generation 2nm-class process is delivering validated gains in power and performance in real customer designs. As mentioned, Synopsys TestMAX™, enhanced with AI-assisted automatic test pattern generation (TSO.ai) and developed in close collaboration with Samsung Foundry, helps reduce test patterns and test cycles by up to 20% while maintaining high fault coverage for both SoC and multi-die designs. These innovations are enabling more efficient, higher-quality silicon development at the most advanced nodes.

Q. Looking ahead, what opportunities do you see for AI-driven design automation and advanced manufacturing technologies to transform semiconductor innovation, particularly for AI, automotive, and high-performance computing applications?

Synopsys’ latest collaborations and innovations highlight a shift toward integrated, system-aware co-design where design decisions are continuously optimised using unified, AI-powered EDA and multiphysics analysis throughout the development lifecycle. This approach enables faster innovation cycles, delivers higher design quality, and drives more efficient use of resources at the most advanced process nodes.