The Package Is the New Processor: Why Chiplets Are Rewriting Semiconductor Design

For most of the industry’s history, progress meant one thing: pack more functions onto a single piece of silicon. That playbook still works for plenty of products. But at the frontier, in AI accelerators, data-centre processors and high-end networking, it is running into hard limits of physics, yield and cost. The response is a quiet but fundamental change in how chips are conceived. Instead of one large die, designers are increasingly building systems from smaller, specialised chiplets that sit together inside a single package.

Stanford’s 2026 Emerging Technology Review lists chiplets among the leading routes to more specialised computing as conventional scaling gets harder. At Semicon Leaders Asia, we think the shift matters for a bigger reason: it moves value and decision-making away from the wafer alone and towards packaging, interconnect standards and system integration. Those are areas where Asia already dominates, and where new Asian players are now trying to get a foothold.

Beyond the single, giant die

A monolithic system-on-chip (SoC) puts compute, memory control, I/O and communications on one die. The trouble is that the biggest dies are now bumping into the reticle limit, the maximum area a lithography scanner can print in one exposure. Big dies are also unforgiving: one defect can scrap an expensive chip, so yields fall sharply as area grows.

Chiplets change the unit of design. A complex system is split into several smaller dies, each handling a defined job, and then reassembled in the package. In a 2.5D design, the chiplets sit side by side on an interposer or bridge that wires them together at very high density. In 3D designs, dies are stacked directly on top of one another.

Example: Nvidia’s Blackwell B200 and B300 accelerators join two large compute dies in one package, linked tightly enough that software sees a single GPU. That was the only practical way to go beyond what one reticle-sized die could hold. Tellingly, when Nvidia was reported in 2025 to be developing the B30A for China, the plan was a single-die version with roughly half the B300’s compute. The number of dies in the package had become a product and policy lever in its own right.

Manufacturing flexibility is the real prize

The most powerful idea behind chiplets is that not every part of a system needs the same manufacturing process. Logic that drives performance can go on the newest, most expensive node. I/O, analogue and memory interfaces, which gain little from shrinking, can use mature and cheaper processes.

Example: AMD has built its EPYC server processors this way for several generations, with compute chiplets on a leading-edge node and a separate I/O die on an older one. Intel went a step further with Meteor Lake, which combined a compute tile made on Intel 4 with graphics, SoC and I/O tiles made by TSMC, stacked together using Intel’s Foveros packaging. One product, two foundries, several nodes.

There is a design advantage too. If one function needs to change, teams can revise that chiplet rather than re-spinning the whole system. Stanford highlights this kind of application-specific optimisation as central to future chip development, and it becomes more valuable as products become more specialised and product cycles shorter.

The cost question is more complicated than it looks

Chiplets are often sold as a cheaper route to complex silicon. The reality is more nuanced. Smaller dies do yield better, and spending advanced-node wafers only where they matter can save real money. But the savings have to pay for new costs: sophisticated packaging, extra testing, known-good-die screening and the engineering needed to make several dies behave as one system. Stanford notes that 2.5D integration adds manufacturing cost even as it adds design flexibility, and one industry cost analysis estimates that chiplet architectures raise total test cost by 15 to 30 per cent compared with monolithic designs.

Example: Packaging choice alone can swing the economics. Reports on Nvidia’s planned B30A noted that its single compute die with four HBM stacks could use TSMC’s simpler CoWoS-S packaging, rather than the more complex CoWoS-L used for the dual-die B200 and B300, helping to lower cost.

Our view: chiplets are not automatically cheaper than a conventional SoC. The case depends on volume, node mix, packaging route and, above all, how much silicon can be reused across products. The right question for a chip company is not “Do chiplets cost less?” but “Does the flexibility we gain justify the packaging and integration bill?”

Interoperability: the make-or-break issue

Once a system contains several dies, they have to talk to each other quickly, efficiently and reliably. Inside one company, that can be solved with a proprietary link. The bigger prize, a genuine market in which chiplets from different vendors can be mixed, requires a common language.

That is the job of Universal Chiplet Interconnect Express (UCIe), an open specification for die-to-die connections within a package. The UCIe 3.0 specification, released in August 2025, doubled data rates to 48 GT/s and 64 GT/s, extended the sideband reach to 100mm for more flexible layouts, added runtime recalibration to save power, and remains backwards compatible with earlier versions. The consortium now counts more than 150 members, and its leadership includes several Asian heavyweights: ASE, Alibaba, Samsung and TSMC. Its current president comes from Samsung Electro-Mechanics.

Asia examples: The UCIe ecosystem is already visibly Asian at the IP level. Taiwan’s InPsytech has shown 3nm UCIe 3.0 technology, Malaysia’s SkyeChip has an advanced-package UCIe 3.0 PHY listed for Samsung’s SF4X process, and Japan’s EdgeCortix has unveiled RAIDEN, an AI chiplet platform aimed at physical AI.

AMD’s open turn shows where the model is heading

AMD has used chiplets for years, but with its own proprietary links. On 25 August 2026 it announced that select Versal RF Series adaptive SoCs will be its first to support native UCIe 1.1 connectivity. The devices will offer up to four UCIe-SP interfaces for standard organic packages and up to two UCIe-AP interfaces for advanced packaging, giving multi-terabit-per-second bandwidth inside the package.

The practical effect is significant. Versal RF devices already combine RF data converters, DSP, AI engines and programmable logic, and AMD says they replace six discrete devices. With UCIe, customers will be able to co-package third-party RF front ends, AI accelerators, CPUs, GPU compute, security engines, communications processors or custom ASICs. AMD expects production chiplets in the fourth quarter of 2027.

The significance is less about one product line and more about the business model. A proven base device plus specialised chiplets, chosen for each application, can replace the old choice between an off-the-shelf part and a costly custom SoC. For radar, satellite communications and test equipment makers, many of which are in Asia, that could shorten development cycles considerably.

Chiplets in practice: five designs worth knowing

Packaging has become architecture

When several dies must work as one, the package stops being the last step in manufacturing and becomes part of the system design. It has to handle die-to-die signalling, power delivery, heat, mechanical stress, reliability and test. Stanford points out that bringing compute and memory closer improves communication but intensifies thermal and integration challenges.

Example, TSMC: TSMC is already producing CoWoS packages with interposers 5.5 times the reticle size, and has set out a 14-reticle version able to integrate about 10 large compute dies and 20 HBM stacks. Analyst estimates put its CoWoS capacity at roughly 120,000 to 130,000 wafers a month by the end of 2026, up from about 13,000 at the end of 2023. These are industry estimates rather than company guidance, but the direction is clear: packaging capacity, not just wafer capacity, now sets the pace of AI hardware supply.

Example, SK hynix: At Hot Chips 2026, SK hynix described how its 16-high HBM3E stack, holding 48GB per cube, forced it to roughly halve chip thickness, gap height and bump pitch to stay within the same height budget, and how hybrid bonding is changing stack assembly. Its message was that HBM packaging is now a co-design problem across bonding, thermals and interposer stress.

Example, materials: Even the substrate is being reinvented. Conventional organic cores expand at 12 to 16 ppm per degree Celsius against roughly 3 for silicon, a mismatch that causes warpage in packages now exceeding 100mm per side. Glass cores are one answer; in July 2026, US materials firm ACCM launched Celeritas SMC, a silicon-matched core designed to run on existing organic-substrate lines.

Design tools are following. At TSMC’s 2026 Open Innovation Platform forum, EDA vendors demonstrated flows for multi-die systems and advanced packaging, including support for systems with hundreds of chiplets, according to the Futurum Group. The opportunity therefore spreads well beyond chip designers, to foundries, OSATs, EDA suppliers, IP vendors, substrate and materials makers, and equipment companies. Research and Markets, for instance, sizes the chiplet assembly equipment market alone at about USD 3.6 billion in 2026, rising to USD 16.2 billion by 2036.

Asia’s chiplet map is being redrawn

Because chiplets shift value into packaging, they also reshuffle national semiconductor strategies. Across the region, the moves are striking:

• Taiwan remains the centre of gravity, with TSMC holding the leading position in advanced 2.5D packaging and OSATs such as ASE and SPIL taking on overflow CoWoS-class work.
• South Korea is pouring capital into packaging. Samsung Electronics has committed 56 trillion won to an HBM fab and packaging facility in the Chungcheong region, while SK hynix has earmarked 20 trillion won of a 100 trillion won Cheongju plan for packaging capacity. Samsung is also deepening ties with Japanese materials and equipment suppliers for large-area chiplet packaging.
• Japan is building back-end capability alongside its 2nm push. Rapidus opened its Rapidus Chiplet Solutions centre in Chitose, Hokkaido, in April 2026 to develop 2. xD and 3D packaging, including hybrid bonding, ahead of planned mass production in 2027. It works with partners including Singapore’s A*STAR IME.
• India is entering through the back end. Tata’s ₹27,120 crore OSAT at Jagiroad, Assam, is designed for about 48 million chips a day; Kaynes Semicon has started commercial OSAT operations in Sanand; and a glass-substrate packaging unit backed by 3D Glass Solutions is coming up in Odisha. Most Indian capacity today is wire-bond and early flip-chip; 2.5D and chiplet integration is the next rung, not the current one.

The takeaway for regional policymakers is that packaging is no longer the “low-value” end of the chain. In a chiplet world, it is where performance, cost and supply security are increasingly decided.

AI is turning up the pressure

AI is not the only reason for chiplets, but it is the strongest accelerant. Training and inference demand huge amounts of compute and, just as importantly, data movement between processors and memory. Stanford’s review ties rising AI demand directly to advances in fabrication, memory and high-bandwidth interconnect. Chiplets let companies combine compute, memory, networking and acceleration in the proportions a particular workload needs.

Market forecasts reflect the momentum, though they should be read with caution. Transparency Market Research expects the chiplet market to grow from about USD 54 billion in 2025 to USD 605 billion by 2036, a 25.2 per cent annual growth rate. Other firms produce very different figures depending on how they define the market, which is itself a sign of how young and fluid the segment is. Several estimates place Asia-Pacific as the largest regional market today, at close to 40 per cent.

The model also travels well beyond AI: automotive compute, industrial systems, communications and aerospace all have mixed workloads and long product lives that suit a modular, reusable approach.

Chiplets will not replace every SoC

None of this spells the end of the monolithic chip. For simpler, high-volume products, one die remains the most efficient answer. Chiplets win when a product needs a mix of specialised functions, very high performance, design flexibility or reuse of proven silicon.

And the hard problems are not solved. Multi-vendor interoperability is still more promise than practice, advanced packaging capacity remains tight, thermal management gets harder with every stacked layer, and test, reliability and liability questions multiply when dies come from different suppliers.

The Semicon Leaders Asia view

The real change is in the designer’s options. The chip is no longer just one large piece of silicon; it is becoming a collection of specialised parts that can be developed, sourced, combined and updated as a system. For the region’s leaders, five things are worth watching over the next 24 months:

• Whether open UCIe chiplets move from announcements into shipping, multi-vendor products, starting with AMD’s Versal RF timeline.
• How fast advanced packaging capacity outside TSMC scales, at OSATs in Taiwan, at Samsung and SK hynix in Korea, and at Rapidus in Japan.
• Whether India’s new OSATs can climb from wire-bond and flip-chip to 2.5D integration within this decade.
• The substrate race between glass cores and new organic alternatives, which will shape the cost of large AI packages.
• Who captures the value of known-good-die testing and chiplet integration, a service layer still up for grabs.

In short, chiplets are less about building bigger chips and more about building the right chip for the job. The companies and the countries that master the package will have a large say in who wins the next decade of semiconductors.